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publication number 23579 revision c amendment 8 issue date december 14, 2005 am29lv320d data sheet retired product this product has been retired and is not avai lable for designs. for new and current designs, s29al032d supersedes am29lv320d and is the fact ory-recommended migration path. please refer to the s29al032d datasheet for specifications and ord ering information. availability of this docu- ment is retained for reference and historical purposes only. april 2005 the following document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these produc ts will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of n ormal datasheet improvement and are noted in the document revision summary, where supported. future routine revisions will occur when appro- priate, and changes will be noted in a revision summary. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions.
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this data sheet states amd?s current technical specif ications regarding the products described herein. this data sheet may be revised by subsequent versions or modi fications due to changes in technical specifications. publication# 23579 rev: c amendment/ 8 issue date: december 14, 2005 refer to amd?s website (www.amd.com) for the latest information. am29lv320d 32 megabit (4 m x 8-bit/2 m x 16-bit) cmos 3.0 volt-only, boot sector flash memory distinctive characteristics architectural advantages ? secured silicon ? 64 kbyte sector size; replacement/substitute devices (such as mirrorbit ? ) have 256 bytes. ? factory locked and identifiable: 16 bytes (8 words) available for secure, random factory electronic serial number; verifiable as factory locked through autoselect function. expressflash option allows entire sector to be availa ble for factory-secured data ? customer lockable: can be programmed once and then permanently locked af ter being shipped from amd ? zero power operation ? sophisticated power mana gement circuits reduce power consumed during inactive periods to nearly zero. ? package options ? 48-pin tsop ?48-ball fbga ? sector architecture ? eight 8 kbyte sectors ? sixty-three 64 kbyte sectors ? top or bottom boot block ? manufactured on 0.23 m process technology ? compatible with jedec standards ? pinout and software compatible with single-power-supply flash standard performance characteristics ? high performance ? access time as fast 90 ns ? program time: 7s/word typical utilizing accelerate function ? ultra low power consumption (typical values) ? 2 ma active read current at 1 mhz ? 10 ma active read current at 5 mhz ? 200 na in standby or automatic sleep mode ? minimum 1 million erase cycles guaranteed per sector ? 20 year data retention at 125c ? reliable operation for the life of the system software features ? supports common flash memory interface (cfi) ? erase suspend/erase resume ? suspends erase operations to allow programming in non-suspended sectors ? data# polling and toggle bits ? provides a software method of detecting the status of program or erase cycles ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences hardware features ? any combination of sectors can be erased ? ready/busy# output (ry/by#) ? hardware method for detec ting program or erase cycle completion ? hardware reset pin (reset#) ? hardware method of resetting the internal state machine to the read mode ? wp#/acc input pin ? write protect (wp#) function allows protection of two outermost boot sector s, regardless of sector protect status ? acceleration (acc) function provides accelerated program times ? sector protection ? hardware method of locking a sector, either in-system or using pr ogramming equipment, to prevent any program or er ase operation within that sector ? temporary sector unprotec t allows changing data in protected sectors in-system this product has been retired and is not available for designs. for new and current designs, s29al032d supersedes am29lv320d an d is the factory-recommended migration path. please refer to the s29al032d datasheet for specifications and ordering information. availability of this document is retained for ref erence and historical purposes only.
2 am29lv320d december 14, 2005 datasheet general description the am29lv320d is a 32 megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. word mode data appears on dq0?dq15; byte mode data appears on dq0?dq7. the device is designed to be programmed in-system with the standard 3.0 volt v cc supply, and can also be programmed in standard eprom programmers. the device is available with an access time of 90 or 120 ns. the devices are offered in 48-pin tsop and 48-ball fbga packages. standard control pins?chip enable (ce#), write enable (we#), and output enable (oe#)?control normal read and write operations, and avoid bus contention issues. the device requires only a single 3.0 volt power sup- ply for both read and write functions. internally gener- ated and regulated voltages are provided for the program and erase operations. am29lv320d features the secured silicon sector is an extra sector capa- ble of being permanently locked by amd or custom- ers. the secured silicon indicator bit (dq7) is permanently set to a 1 if the part is factory locked , and set to a 0 if customer lockable . this way, cus- tomer lockable parts can never be used to replace a factory locked part. note that the am29lv320d has a secured silicon sector size of 64 kbytes. amd devices designated as replacements or substi- tutes, such as the am29lv320m, have 256 bytes. this should be considered during system design. factory locked parts provide several options. the se- cured silicon sector may store a secure, random 16 byte esn (electronic serial number), customer code (programmed through amd?s expressflash service), or both. customer lockable parts may utilize the se- cured silicon sector as bonus space, reading and writ- ing like any other flash sector, or may permanently lock their own code there. the device offers comple te compatibility with the jedec single-power-supply flash command set standard . commands are written to the command register using standard microprocessor write timings. reading data out of the device is similar to reading from other flash or eprom devices. the host system can detect whether a program or erase operation is complete by using the device sta- tus bits: ry/by# pin, dq7 (data# polling) and dq6/dq2 (toggle bits). after a program or erase cycle is completed, the device automatically returns to the read mode. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. this can be achieved in-system or via program- ming equipment. the device offers two power-saving features. when addresses are stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both modes.
december 14, 2005 am29lv320d 3 datasheet table of contents continuity of specificat ions ....................................................... i for more information ................................................................. i distinctive characteristics . . . . . . . . . . . . . . . . . . 1 architectural advantages ...................................... 1 performance characteristics ............................... 1 software features ..................................................... 1 hardware features .................................................... 1 general description . . . . . . . . . . . . . . . . . . . . . . . 2 product selector guide . . . . . . . . . . . . . . . . . . . . . 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . 6 special package ha ndling instructions .................................... 7 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ordering information . . . . . . . . . . . . . . . . . . . . . . . 9 device bus operations . . . . . . . . . . . . . . . . . . . . . 10 table 1. am29lv320d device bus operations ..............................10 word/byte configuration ........................................................ 11 requirements for reading array data ................................... 11 writing commands/command sequences ............................ 11 accelerated prog ram operation .......................................... 11 autoselect functions ........................................................... 11 standby mode ........................................................................ 12 automatic sleep mode ........................................................... 12 reset#: hardware reset pin ............................................... 12 output disable mode .............................................................. 12 table 2. top boot sector addresses (am29lv320dt) ..................13 table 3. top boot secured sili con sector addresses ................... 14 table 4. bottom boot sector addresses (am29lv320db) .............14 table 5. bottom boot secured si licon sector addresses .............. 15 autoselect mode ..................................................................... 16 table 6. autoselect codes (high voltage method) ........................16 sector/sector block protection and unprotection .................. 17 table 7. top boot sector/sector block addresses for protection/unprotection .............................................................17 table 8. bottom boot sector/sector block addresses for protection/unprotection ...........................................17 write protect (wp#) ................................................................ 18 temporary sector unprotect .................................................. 18 figure 1. temporary sector unprotect operation........................... 18 figure 2. in-system sector pr otect/unprotect algorithms .............. 19 secured silicon sector flas h memory region ....................... 20 factory locked: secured silicon sector programmed and protected at the factory ............................................... 20 customer lockable: secured si licon sector not programmed or protected at the factory .................................................. 20 figure 3. secured silicon sector protect verify .............................. 21 hardware data protection ...................................................... 21 low vcc write inhibit ......................................................... 21 write pulse ?glitch? protection ............................................ 21 logical inhibit ...................................................................... 21 power-up write inhibit ......................................................... 21 common flash memory interfac e (cfi) . . . . . . . 21 table 9. cfi query identification string .......................................... 22 table 10. system interface string................................................... 22 table 11. device geometry definition ............................................ 23 table 12. primary v endor-specific extended query ...................... 24 command definitions . . . . . . . . . . . . . . . . . . . . . . 25 reading array data ................................................................ 25 reset command ..................................................................... 25 autoselect command sequence ............................................ 25 table 13. autoselect codes ........................................................... 25 enter secured silicon sector/e xit secured silicon sector command sequence .............................................................. 25 byte/word program comma nd sequence ............................. 26 unlock bypass command sequence .................................. 26 figure 4. program operation ......................................................... 27 chip erase command sequence ........................................... 27 sector erase command s equence ........................................ 27 erase suspend/erase resu me commands ........................... 28 figure 5. erase operation.............................................................. 28 command defini tions ............................................................. 29 table 14. am29lv320d command definitions ............................. 29 write operation status . . . . . . . . . . . . . . . . . . . . 30 dq7: data# polling ................................................................. 30 figure 6. data# polling algorithm .................................................. 30 ry/by#: ready/busy# ............................................................ 31 dq6: toggle bit i .................................................................... 31 figure 7. toggle bit algorithm........................................................ 31 dq2: toggle bit ii ................................................................... 31 reading toggle bi ts dq6/dq2 ............................................... 32 dq5: exceeded timing limits ................................................ 32 dq3: sector erase timer ....................................................... 32 table 15. write operation status ................................................... 33 absolute maximum ratings . . . . . . . . . . . . . . . . 34 figure 8. maximum negative overshoot waveform ...................... 34 figure 9. maximum positive overshoot waveform........................ 34 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . 34 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35 cmos compatible .................................................................. 35 zero-power flash ................................................................. 36 figure 10. i cc1 current vs. time (showing active and automatic sleep currents) ............................................................. 36 figure 11. typical i cc1 vs. frequency ............................................ 36 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 12. test setup.................................................................... 37 table 16. test specifications ......................................................... 37 figure 13. input waveforms and measurement levels ................. 37 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38 read-only operations ........................................................... 38 figure 14. read operation timings ............................................... 38 hardware reset (reset#) .................................................... 39 figure 15. reset timings ............................................................... 39 word/byte configuration (byte#) ............................................. 40 figure 16. byte# timings for read operations............................ 40 figure 17. byte# timings for write operations............................ 40 erase and progra m operations ................................................. 41 figure 18. program operation timings.......................................... 42 figure 19. chip/sector erase operation timings .......................... 43 figure 20. data# polling timings (during embedded algorithms). 44 figure 21. toggle bit timings (during embedded algorithms)...... 45 figure 22. dq2 vs. dq6................................................................. 45 temporary sector unprotect ..................................................... 46 figure 23. temporary sector u nprotect timing diagram .............. 46 figure 24. accelerated program timing diagram.......................... 46 figure 25. sector/sector block protect and unprotect timing diagram ............................................................. 47 alternate ce# controlled eras e and program operations ........ 48 figure 26. alternate ce# controlled write
4 am29lv320d december 14, 2005 datasheet (erase/program) operation timings ............................................... 49 erase and programming performance . . . . . . . . 50 latchup characteristics . . . . . . . . . . . . . . . . . . . 50 tsop and bga package capacitance . . . . . . . 50 data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 51 fbd048?48-ball fine-pitch ball grid array (fbga) 6 x 12 mm package ................................................................... 51 ts 048?48-pin standard ts op ............................................... 52 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 53 ordering information ............................................................ 53 connection diagrams .......................................................... 53 global .................................................................................. 53 table 3, top boot secured silicon sector addresses ......... 53 sector/sector block protection and unprotection ............... 53 secured silicon sector flash memory region .................... 53 global .................................................................................. 53 ordering information ............................................................ 53 table 1, am29lv320d device bus operations ................... 53 secured silicon sector flash memory region .................... 53 autoselect command sequence ......................................... 53 table 14, am29lv320d command definitions ................... 53 erase and program operations table .................................. 53 figure 3, secured silicon sector protect verify ................... 53 distinctive characteristics ................................................... 53 connection diagrams .......................................................... 53 ordering information ............................................................ 53 secured silicon flash memo ry region ............................... 53 command definitions .......................................................... 53 ac characteristics ............................................................... 53 dc characteristics ............................................................... 53 tsop, so, and bga package capacitance ....................... 53 distinctive characteristics ................................................... 53 secured silicon flash memo ry region ............................... 53 command definitions .......................................................... 54 erase and programming performance ................................ 54 distinctive characteristics ................................................... 54 secured silicon sector ........................................................ 54 valid combinations .............................................................. 54 command definitions .......................................................... 54 ordering information ............................................................ 54 product selector guide ....................................................... 54 global .................................................................................. 54 ordering information ............................................................ 54 erase and programming performance ................................ 54 ac characteristics ............................................................... 54 erase and program operations ........................................... 54 alternate ce# control erase and program operations ....... 54 command definitions .......................................................... 54 global .................................................................................. 54 common flash memory interfacte (cfi) ............................. 54 global .................................................................................. 54
december 14, 2005 am29lv320d 5 datasheet product selector guide block diagram family part number am29lv320d speed option standard voltage range: v cc = 2.7?3.6 v 90r standard voltage range: v cc = 3.0?3.6 v 90 120 max access time (ns) 90 120 ce# access (ns) 90 120 oe# access (ns) 40 50 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# byte# ce# oe# stb stb dq0 ? dq15 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a0?a20
6 am29lv320d december 14, 2005 datasheet connection diagrams 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 a18 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# nc wp#/acc ry/by# a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 48-pin standard tsop
december 14, 2005 am29lv320d 7 datasheet connection diagrams special package handling instructions special handling is required for flash memory prod- ucts in molded (tsop, bga) packages. the package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150 c for prolonged periods of time. a1 b1 c1 d1 e1 f1 g1 h1 a2 b2 c2 d2 e2 f2 g2 h2 a3 b3 c3 d3 e3 f3 g3 h3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 dq15/a-1 v ss byte# a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 nc reset# we# dq11 dq3 dq10 dq2 a20 a18 wp#/acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 48-ball fbga top view, balls facing down
8 am29lv320d december 14, 2005 datasheet pin description a0?a20 = 21 addresses dq0?dq14 = 15 data inputs/outputs dq15/a-1 = dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# = chip enable oe# = output enable we# = write enable wp#/acc = hardware write protect/ acceleration pin reset# = hardware reset pin, active low byte# = selects 8-bit or 16-bit mode ry/by# = ready/busy output v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v ss = device ground nc = pin not connected internally logic symbol 21 16 or 8 dq0?dq15 (a-1) a0?a20 ce# oe# we# reset# byte# ry/by# wp#/acc
december 14, 2005 am29lv320d 9 datasheet ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. am29lv320d t 90 e c temperature range i = industrial (?40 c to +85 c) f = industrial (?40 c to +85 c) with pb-free package c = commercial (0 c to +70 c) d = commercial (0 c to +70 c) with pb-free package v = automotive in-cabin (-40 c to +105 c) y = automotive in-cabin (-40 c to +105 c ) with pb-free package package type e = 48-pin thin small outline package (tsop) standard pinout (ts 048) wm = 48-ball fine-pitch ball grid array (fbga) 0.80 mm pitch, 6 x 12 mm package (fbd048) speed option see product selector guide and valid combinations boot code sector architecture t = top boot sector b = bottom boot sector device number/description am29lv320d 32 megabit (4 m x 8-bit/2 m x 16-bit) cmos boot sector flash memory 3.0 volt-only read, program and erase valid combinations for tsop packages speed (ns) v cc range am29lv320dt90r, am29lv320db90r ec, ei, ed, ef 90 3.0? 3.6v am29lv320dt90, am29lv320db90 90 2.7? 3.6v am29lv320dt120, am29lv320db120 120 2.7? 3.6v am29lv320dt120 am29lv320db120 ev, ey 120 2.7 ? 3,6v valid combinations for fbga packages order number package marking am29lv320dt90, am29lv320db90 wmc, wmi, wmd, wmf l320dt90v, l320db90v c, i, d, f am29lv320dt120, am29lv320db120 l320dt12v, l320db12v am29lv320dt120 am29lv320db120 wnv l320dt12v l320db12v v, y
10 am29lv320d december 14, 2005 datasheet device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. am29lv320d device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 11.5?12.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are a20:a0 in word mode (byte# = v ih ), a20:a-1 in byte mode (byte# = v il ). 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see ?sector/sector block protection and unprotection? on page 17. 3. if wp#/acc = v il , the two outermost boot sectors re main protected. if wp#/acc = v ih , the two outermost boot sector protection depends on whether they were last protect ed or unprotected using the method described in ?sector/ sector block protection and unprotection? on page 17. if wp#/acc = v hh , all sectors are unprotected. 4. d in or d out as required by command sequence, data po lling, or sector protection algorithm. operation ce# oe# we# reset# wp#/acc addresses (note 2) dq0? dq7 dq8?dq15 byte# = v ih byte# = v il read l l h h l/h a in d out d out dq8?dq14 = high-z, dq15 = a-1 write l h l h (note 3) a in (note 4) (note 4) accelerated program l h l h v hh a in (note 4) (note 4) standby v cc 0.3 v xx v cc 0.3 v h x high-z high-z high-z output disable l h h h l/h x high-z high-z high-z reset x x x l l/h x high-z high-z high-z sector protect (note 2) l h l v id l/h sa, a6 = l, a1 = h, a0 = l (note 4) x x sector unprotect (note 2) lhl v id (note 3) sa, a6 = h, a1 = h, a0 = l (note 4) x x temporary sector unprotect xxx v id (note 3) a in (note 4) (note 4) high-z
december 14, 2005 am29lv320d 11 datasheet word/byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte# pin is set at logic ?1?, the device is in word con- figuration, dq0?dq15 are active and controlled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is in byte configuration, and only data i/o pins dq0?dq7 are active and controlled by ce# and oe#. the data i/o pins dq8?dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output con- trol and gates array data to the output pins. we# should remain at v ih . the byte# pin determines whether the device outputs array data in words or bytes. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?requirements for reading array data? on page 11 for more information. refer to the ac read-only operations table for timing specifications and to figure 14, on page 38 for the timing diagram. i cc1 in the dc characteristics table represents the ac- tive current specification for reading array data. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . for program operations, the byte# pin determines whether the device accepts program data in bytes or words. refer to ?word/byte configuration? on page 11 for more information. the device features an unlock bypass mode to facili- tate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. the ?word/byte configuration? on page 11 section con- tains details on programming data to the device using both standard and unlock bypass command se- quences. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 2 on page 13 through table 5 on page 15 indicate the address space that each sector occupies. a ?sector address? is the ad- dress bits required to uniquely select a sector. i cc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the ?ac characteristics? on page 38 section contains timing specification tables and timing diagrams for write oper- ations. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc pin. this function is prima- rily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device auto- matically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin returns the device to nor- mal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated program- ming, or device damage may result. in addition, the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the ?autoselect mode? on page 16 and ?autoselect command sequence? on page 25 sections for more information. i cc6 and i cc7 in the dc characteristics table represent the current specifications for read-while-program and read-while-erase, respectively.
12 am29lv320d december 14, 2005 datasheet standby mode when the system is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device is in the standby mode, but the standby current is greater. the device requires stan- dard access time (t ce ) for read access when the de- vice is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. i cc3 in the dc characteristics table represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard ad- dress access timings provide new data when ad- dresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the ?dc characteristics? on page 35 table rep- resents the automatic sleep mode current specifica- tion. reset#: hardware reset pin the reset# pin provides a hardware method of re- setting the device to reading array data. when the re- set# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. current is reduced for th e duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current is greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. if reset# is asserted during a program or erase op- eration, the ry/by# pin remains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the sys- tem can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algo- rithms). the system can read data t rh after the re- set# pin returns to v ih . refer to the ac characteristics tables for reset# pa- rameters and to figure 15, on page 39 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state.
december 14, 2005 am29lv320d 13 datasheet table 2. top boot sector addresses (am29lv320dt) (sheet 1 of 2) sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 000000xxx 64/32 000000h?00ffffh 000000h?07fffh sa1 000001xxx 64/32 010000h?01ffffh 008000h?0ffffh sa2 000010xxx 64/32 020000h?02ffffh 010000h?17fffh sa3 000011xxx 64/32 030000h?03ffffh 018000h?01ffffh sa4 000100xxx 64/32 040000h?04ffffh 020000h?027fffh sa5 000101xxx 64/32 050000h?05ffffh 028000h?02ffffh sa6 000110xxx 64/32 060000h?06ffffh 030000h?037fffh sa7 000111xxx 64/32 070000h?07ffffh 038000h?03ffffh sa8 001000xxx 64/32 080000h?08ffffh 040000h?047fffh sa9 001001xxx 64/32 090000h?09ffffh 048000h?04ffffh sa10 001010xxx 64/32 0a0000h?0affffh 050000h?057fffh sa11 001011xxx 64/32 0b0000h?0bffffh 058000h?05ffffh sa12 001100xxx 64/32 0c0000h?0cffffh 060000h?067fffh sa13 001101xxx 64/32 0d0000h?0dffffh 068000h?06ffffh sa14 001110xxx 64/32 0e0000h?0effffh 070000h?077fffh sa15 001111xxx 64/32 0f0000h?0fffffh 078000h?07ffffh sa16 010000xxx 64/32 100000h?10ffffh 080000h?087fffh sa17 010001xxx 64/32 110000h?11ffffh 088000h?08ffffh sa18 010010xxx 64/32 120000h?12ffffh 090000h?097fffh sa19 010011xxx 64/32 130000h?13ffffh 098000h?09ffffh sa20 010100xxx 64/32 140000h?14ffffh 0a0000h?0a7fffh sa21 010101xxx 64/32 150000h?15ffffh 0a8000h?0affffh sa22 010110xxx 64/32 160000h?16ffffh 0b0000h?0b7fffh sa23 010111xxx 64/32 170000h?17ffffh 0b8000h?0bffffh sa24 011000xxx 64/32 180000h?18ffffh 0c0000h?0c7fffh sa25 011001xxx 64/32 190000h?19ffffh 0c8000h?0cffffh sa26 011010xxx 64/32 1a0000h?1affffh 0d0000h?0d7fffh sa27 011011xxx 64/32 1b0000h?1bffffh 0d8000h?0dffffh sa28 011100xxx 64/32 1c0000h?1cffffh 0e0000h?0e7fffh sa29 011101xxx 64/32 1d0000h?1dffffh 0e8000h?0effffh sa30 011110xxx 64/32 1e0000h?1effffh 0f0000h?0f7fffh sa31 011111xxx 64/32 1f0000h?1fffffh 0f8000h?0fffffh sa32 100000xxx 64/32 200000h?20ffffh 100000h?107fffh sa33 100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa34 100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa35 100011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa36 100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa37 100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa38 100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa39 100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa40 101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa41 101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa42 101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa43 101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa44 101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa45 101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa46 101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa47 101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa48 110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa49 110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa50 110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa51 110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa52 110100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh
14 am29lv320d december 14, 2005 datasheet note: the address range is a20:a-1 in byte mode (byte#=v il ) or a20:a0 in word mode (byte#=v ih ). table 3. top boot secured silicon sector addresses sa53 110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa54 110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa55 110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa56 111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa57 111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa58 111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa59 111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa60 111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa61 111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa62 111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa63 111111000 8/4 3f0000h?3f1fffh 1f8000h?1f8fffh sa64 111111001 8/4 3f2000h?3f3fffh 1f9000h?1f9fffh sa65 111111010 8/4 3f4000h?3f5fffh 1fa000h?1fafffh sa66 111111011 8/4 3f6000h?3f7fffh 1fb000h?1fbfffh sa67 111111100 8/4 3f8000h?3f9fffh 1fc000h?1fcfffh sa68 111111101 8/4 3fa000h?3fbfffh 1fd000h?1fdfffh sa69 111111110 8/4 3fc000h?3fdfffh 1fe000h?1fefffh sa70 111111111 8/4 3fe000h?3fffffh 1ff000h?1fffffh table 2. top boot sector addresses (am29lv320dt) (sheet 2 of 2) sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range 111111xxx 64/32 3f0000h?3fffffh 1f8000h?1fffffh table 4. bottom boot sector addresses (am29lv320db) (sheet 1 of 2) sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 000000000 8/4 000000h-001fffh 000000h?000fffh sa1 000000001 8/4 002000h-003fffh 001000h?001fffh sa2 000000010 8/4 004000h-005fffh 002000h?002fffh sa3 000000011 8/4 006000h-007fffh 003000h?003fffh sa4 000000100 8/4 008000h-009fffh 004000h?004fffh sa5 000000101 8/4 00a000h-00bfffh 005000h?005fffh sa6 000000110 8/4 00c000h-00dfffh 006000h?006fffh sa7 000000111 8/4 00e000h-00ffffh 007000h?007fffh sa8 000001xxx 64/32 010000h-01ffffh 008000h?00ffffh sa9 000010xxx 64/32 020000h-02ffffh 010000h?017fffh sa10 000011xxx 64/32 030000h-03ffffh 018000h?01ffffh sa11 000100xxx 64/32 040000h-04ffffh 020000h?027fffh sa12 000101xxx 64/32 050000h-05ffffh 028000h?02ffffh sa13 000110xxx 64/32 060000h-06ffffh 030000h?037fffh sa14 000111xxx 64/32 070000h-07ffffh 038000h?03ffffh sa15 001000xxx 64/32 080000h-08ffffh 040000h?047fffh sa16 001001xxx 64/32 090000h-09ffffh 048000h?04ffffh sa17 001010xxx 64/32 0a0000h-0affffh 050000h?057fffh sa18 001011xxx 64/32 0b0000h-0bffffh 058000h?05ffffh sa19 001100xxx 64/32 0c0000h-0cffffh 060000h?067fffh sa20 001101xxx 64/32 0d0000h-0dffffh 068000h?06ffffh sa21 001110xxx 64/32 0e0000h-0effffh 070000h?077fffh sa22 001111xxx 64/32 0f0000h-0fffffh 078000h?07ffffh sa23 010000xxx 64/32 100000h-10ffffh 080000h?087fffh sa24 010001xxx 64/32 110000h-11ffffh 088000h?08ffffh sa25 010010xxx 64/32 120000h-12ffffh 090000h?097fffh sa26 010011xxx 64/32 130000h-13ffffh 098000h?09ffffh sa27 010100xxx 64/32 140000h-14ffffh 0a0000h?0a7fffh sa28 010101xxx 64/32 150000h-15ffffh 0a8000h?0affffh sa29 010110xxx 64/32 160000h-16ffffh 0b0000h?0b7fffh
december 14, 2005 am29lv320d 15 datasheet note: the address range is a20:a-1 in byte mode (byte#=v il ) or a20:a0 in word mode (byte#=v ih ). table 5. bottom boot secured silicon sector addresses sa30 010111xxx 64/32 170000h-17ffffh 0b8000h?0bffffh sa31 011000xxx 64/32 180000h-18ffffh 0c0000h?0c7fffh sa32 011001xxx 64/32 190000h-19ffffh 0c8000h?0cffffh sa33 011010xxx 64/32 1a0000h-1affffh 0d0000h?0d7fffh sa34 011011xxx 64/32 1b0000h-1bffffh 0d8000h?0dffffh sa35 011100xxx 64/32 1c0000h-1cffffh 0e0000h?0e7fffh sa36 011101xxx 64/32 1d0000h-1dffffh 0e8000h?0effffh sa37 011110xxx 64/32 1e0000h-1effffh 0f0000h?0f7fffh sa38 011111xxx 64/32 1f0000h-1fffffh 0f8000h?0fffffh sa39 100000xxx 64/32 200000h-20ffffh 100000h?107fffh sa40 100001xxx 64/32 210000h-21ffffh 108000h?10ffffh sa41 100010xxx 64/32 220000h-22ffffh 110000h?117fffh sa42 100011xxx 64/32 230000h-23ffffh 118000h?11ffffh sa43 100100xxx 64/32 240000h-24ffffh 120000h?127fffh sa44 100101xxx 64/32 250000h-25ffffh 128000h?12ffffh sa45 100110xxx 64/32 260000h-26ffffh 130000h?137fffh sa46 100111xxx 64/32 270000h-27ffffh 138000h?13ffffh sa47 101000xxx 64/32 280000h-28ffffh 140000h?147fffh sa48 101001xxx 64/32 290000h-29ffffh 148000h?14ffffh sa49 101010xxx 64/32 2a0000h-2affffh 150000h?157fffh sa50 101011xxx 64/32 2b0000h-2bffffh 158000h?15ffffh sa51 101100xxx 64/32 2c0000h-2cffffh 160000h?167fffh sa52 101101xxx 64/32 2d0000h-2dffffh 168000h?16ffffh sa53 101110xxx 64/32 2e0000h-2effffh 170000h?177fffh sa54 101111xxx 64/32 2f0000h-2fffffh 178000h?17ffffh sa55 111000xxx 64/32 300000h-30ffffh 180000h?187fffh sa56 110001xxx 64/32 310000h-31ffffh 188000h?18ffffh sa57 110010xxx 64/32 320000h-32ffffh 190000h?197fffh sa58 110011xxx 64/32 330000h-33ffffh 198000h?19ffffh sa59 110100xxx 64/32 340000h-34ffffh 1a0000h?1a7fffh sa60 110101xxx 64/32 350000h-35ffffh 1a8000h?1affffh sa61 110110xxx 64/32 360000h-36ffffh 1b0000h?1b7fffh sa62 110111xxx 64/32 370000h-37ffffh 1b8000h?1bffffh sa63 111000xxx 64/32 380000h-38ffffh 1c0000h?1c7fffh sa64 111001xxx 64/32 390000h-39ffffh 1c8000h?1cffffh sa65 111010xxx 64/32 3a0000h-3affffh 1d0000h?1d7fffh sa66 111011xxx 64/32 3b0000h-3bffffh 1d8000h?1dffffh sa67 111100xxx 64/32 3c0000h-3cffffh 1e0000h?1e7fffh sa68 111101xxx 64/32 3d0000h-3dffffh 1e8000h?1effffh sa69 111110xxx 64/32 3e0000h-3effffh 1f0000h?1f7fffh sa70 111111xxx 64/32 3f0000h-3fffffh 1f8000h?1fffffh sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range 000000xxx 64/32 000000h-00ffffh 00000h-07fffh table 4. bottom boot sector addresses (am29lv320db) (sheet 2 of 2) sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
16 am29lv320d december 14, 2005 datasheet autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equip- ment to automatically match a device to be pro- grammed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (11.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in table 6 on page 16. in addition, when verifying sector protection, the sector address must appear on the ap- propriate highest order address bits (see table 2 on page 13 through table 5 on page 15). table 6 on page 16 shows the remaining address bits that are don?t care. when all necessary bits are set as re- quired, the programming equipment may then read the corresponding identifier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 14 on page 29. this method does not require v id . refer to the ?au- toselect command sequence? on page 25 section for more information. table 6. autoselect codes (high voltage method) legend: t = top boot block, b = bottom boot block, l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. description ce# oe# we# a20 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq8 to dq15 dq7 to dq0 byte#= v ih byte# = v il manufacturer id : amd l l h x x v id xlxll x x 01h device id: am29lv320d l l h x x v id x l x l h 22h x f6 (t), f9h (b) sector protection verification l l h sa x v id xlxhl x x 01h (protected), 00h (unprotected) secured silicon sector indicator bit (dq7) llh x x v id xlxhh x x 99h (factory locked), 19h (not factory locked)
december 14, 2005 am29lv320d 17 datasheet sector/sector block protection and unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hard- ware sector unprotection feature re-enables both pro- gram and erase operations in previously protected sectors. sector protection/unprotection can be imple- mented via two methods. (note: for the following discussion, the term ?sector? applies to both sectors and sector blocks. a sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see table 7 on page 17 and table 8 on page 17). table 7. top boot sector/sector block addresses for protection/unprotection table 8. bottom boot sector/sector block addresses for protection/unprotection sector protection and unprotection requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 2, on page 19 shows the algorithms and figure 25, on page 47 shows the timing diagram. this method uses stan- dard microprocessor bus cycle timing. for sector un- protect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. the sector unprotect algorithm unprotects all sectors in parallel. all previously protected sectors must be in- dividually re-protected. to change data in protected sectors efficiently, the temporary sector unprotect function is available. see ?temporary sector unpro- tect? on page 18 . the alternate method intended only for programming equipment, and requires v id on address pin a9 and oe#. this method is compatible with programmer rou- tines written for earlier 3.0 volt-only amd flash de- vices. for detailed information, contact an amd representative. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at its factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is pro- tected or unprotected. see ?autoselect mode? on page 16 for details. sector / sector block a20?a12 sector/sector block size sa0-sa3 000000xxx, 000001xxx, 000010xxx 000011xxx 256 (4x64) kbytes sa4-sa7 0001xxxxx 256 (4x64) kbytes sa8-sa11 0010xxxxx 256 (4x64) kbytes sa12-sa15 0011xxxxx 256 (4x64) kbytes sa16-sa19 0100xxxxx 256 (4x64) kbytes sa20-sa23 0101xxxxx 256 (4x64) kbytes sa24-sa27 0110xxxxx 256 (4x64) kbytes sa28-sa31 0111xxxxx 256 (4x64) kbytes sa32-sa35 1000xxxxx 256 (4x64) kbytes sa36-sa39 1001xxxxx 256 (4x64) kbytes sa40-sa43 1010xxxxx 256 (4x64) kbytes sa44-sa47 1011xxxxx 256 (4x64) kbytes sa48-sa51 1100xxxxx 256 (4x64) kbytes sa52-sa55 1101xxxxx 256 (4x64) kbytes sa56-sa59 1110xxxxx 256 (4x64) kbytes sa60-sa62 111100xxx, 111101xxx, 111110xxx 192 (3x64) kbytes sa63 111111000 8 kbytes sa64 111111001 8 kbytes sa65 111111010 8 kbytes sa66 111111011 8 kbytes sa67 111111100 8 kbytes sa68 111111101 8 kbytes sa69 111111110 8 kbytes sa70 111111111 8 kbytes sector / sector block a20?a12 sector/sector block size sa70-sa67 111111xxx, 111110xxx, 111101xxx, 111100xxx 256 (4x64) kbytes sa66-sa63 1110xxxxx 256 (4x64) kbytes sa62-sa59 1101xxxxx 256 (4x64) kbytes sa58-sa55 1100xxxxx 256 (4x64) kbytes sa54-sa51 1011xxxxx 256 (4x64) kbytes sa50-sa47 1010xxxxx 256 (4x64) kbytes sa46-sa43 1001xxxxx 256 (4x64) kbytes sa42-sa39 1000xxxxx 256 (4x64) kbytes sa38-sa35 0111xxxxx 256 (4x64) kbytes sa34-sa31 0110xxxxx 256 (4x64) kbytes sa30-sa27 0101xxxxx 256 (4x64) kbytes sa26-sa23 0100xxxxx 256 (4x64) kbytes sa22?sa19 0011xxxxx 256 (4x64) kbytes sa18-sa15 0010xxxxx 256 (4x64) kbytes sa14-sa11 0001xxxxx 256 (4x64) kbytes sa10-sa8 000011xxx, 000010xxx, 000001xxx 192 (3x64) kbytes sa7 000000111 8 kbytes sa6 000000110 8 kbytes sa5 000000101 8 kbytes sa4 000000100 8 kbytes sa3 000000011 8 kbytes sa2 000000010 8 kbytes sa1 000000001 8 kbytes sa0 000000000 8 kbytes sector / sector block a20?a12 sector/sector block size
18 am29lv320d december 14, 2005 datasheet write protect (wp#) the write protect function provides a hardware method of protecting certain boot sectors without using v id . this function is one of two provided by the wp#/acc pin. if the system asserts v il on the wp#/acc pin, the de- vice disables program and erase functions in the two ?outermost? 8 kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in ?sector/sector block protection and unprotection? on page 17. the two out- ermost 8 kbyte boot sectors are the two sectors con- taining the lowest addresses in a bottom-boot-configured device, or the two sectors con- taining the highest addresses in a top-boot-configured device. if the system asserts v ih on the wp#/acc pin, the de- vice reverts to whether the two outermost 8k byte boot sectors were last set to be protected or unpro- tected. that is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in ?sector/sector block protection and unprotection? on page 17. note that the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. temporary sector unprotect this feature allows temporary unprotection of previ- ously protected sectors to change data in-system. the sector unprotect mode is activated by setting the re- set# pin to v id (11.5 v ? 12.5 v). during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the previously pro- tected sectors are protected again. figure 1, on page 18 shows the algorithm, and figure 23, on page 46 shows the timing diagrams, for this feature. figure 1. temporary sector unprotect operation start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sectors unprotected (if wp#/acc = v il , outermost boot sectors remain protected). 2. all previously protected sectors are protected once again.
december 14, 2005 am29lv320d 19 datasheet figure 2. in-system sector protect/unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 ? verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
20 am29lv320d december 14, 2005 datasheet secured silicon sect or flash memory region the secured silicon sector provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the se- cured silicon sector uses a secured silicon indicator bit (dq7) to indicate whether or not the secured sili- con sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the security of the esn once the product is shipped to the field. note that the am29lv320d has a secured silicon sector size of 64 kbytes. amd devices designated as replace- ments or substitutes, such as the am29lv320m, have 256 bytes. this should be considered during system design. amd offers the device with the secured silicon sector either factory locked or customer lockable. the fac- tory-locked version is always protected when shipped from the factory, and has the secured silicon sector indicator bit permanently set to a ?1.? the cus- tomer-lockable version is shipped with the secured silicon sector unprotected, allowing customers to uti- lize the that sector in any manner they choose. the customer-lockable version has the secured silicon in- dicator bit permanently set to a ?0.? thus, the secured silicon indicator bit prevents customer-lockable de- vices from being used to replace devices that are fac- tory locked. the system accesses the secured silicon sector through a command sequence (see ?enter secured silicon sector/exit secured silicon sector command sequence? on page 25). after the system writes the enter secured silicon sector command se- quence, it may read the secured silicon sector by using the addresses normally occupied by the boot sectors. this mode of operation continues until the system issues the exit secured silicon sector com- mand sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. factory locked: secured silicon sector programmed and protected at the factory in a factory locked device, the secured silicon sector is protected when the device is shipped from the fac- tory. the secured silicon sector cannot be modified in any way. the device is available preprogrammed with one of the following: a random, secure esn only customer code through the expressflash service both a random, secure esn and customer code through the expressflash service. in devices that have an esn, a bottom boot device has the 16-byte (8-word) esn in sector 0 at addresses 00000h?0000fh in byte mode (or 00000h?00007h in word mode). in the top boot device the esn is in sec- tor 63 at addresses 3f0000h?3f000fh in byte mode (or 1f8000h?1f8007h in word mode). note that in up- coming top boot versions of this device, the esn is lo- cated in sector 70 at addresses 3fe000h?3fe00fh in byte mode (or 1ff000h?1ff007h in word mode). customers may opt to have their code programmed by amd through the amd expressflash service. amd programs the customer?s code, with or without the ran- dom esn. the devices are then shipped from amd?s factory with the secured silicon sector permanently locked. contact an amd representative for details on using amd?s expressflash service. customer lockable: secured silicon sector not programmed or protected at the factory the customer lockable version allows the secured sil- icon sector to be programmed once and then perma- nently locked after it ships from amd. note that the am29lv320d has a secured silicon sector size of 64 kbytes. amd devices designated as replace- ments or substitutes, such as the am29lv320m, have 256 bytes. this should be considered during system design. additionally, note the change in the location of the esn in upcoming top boot fac- tory locked devices. note that the accelerated pro- gramming (acc) and unlock bypass functions are not available when programming the secured silicon sec- tor. the secured silicon sector area can be protected using the following procedures: write the three-cycle enter secured silicon sector command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, on page 19 , except that reset# may be at either v ih or v id . this allows in-system protection of the se- cured silicon sector without raising any device pin to a high voltage. note that this method is only ap- plicable to the secured silicon sector. to verify the protect/unprotect status of the secured silicon sector, follow the algorithm shown in figure 3, on page 21 . once the secured silicon sector is locked and veri- fied, the system must write the exit secured silicon sector command sequence to return to reading and writing the remainder of the array. the secured silicon sector protection must be used with caution since, once protected, there is no proce- dure available for unprotecting the secured silicon sector area and none of the bits in the secured silicon sector memory space can be modified in any way.
december 14, 2005 am29lv320d 21 datasheet figure 3. secured silicon sector protect verify hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 14 on page 29 for command definitions). in addition, the fol- lowing hardware data protection measures prevent ac- cidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the sys- tem writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the sys- tem can read cfi information at the addresses given in table 9 on page 22 through table 12 on page 24. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in table 9 on page 22 through table 12 on page 24. the system must write the reset command to return the device to the reading array data. for further information, please refer to the cfi specifi- cation, cfi publication 100, and the application note ?common flash interface version 1.4 vendor specific extensions?. contact an amd representative for cop- ies of these documents. write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 s read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
22 am29lv320d december 14, 2005 datasheet table 9. cfi query identification string table 10. system interface string addresses (word mode) addresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) addresses (word mode) addresses (byte mode) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0004h typical timeout per single byte/word write 2 n s 20h 40h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2 n times typical 24h 48h 0000h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
december 14, 2005 am29lv320d 23 datasheet table 11. device geometry definition addresses (word mode) addresses (byte mode) data description 27h 4eh 0016h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0000h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 58h 0002h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 003eh 0000h 0000h 0001h erase block region 2 information 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information
24 am29lv320d december 14, 2005 datasheet table 12. primary vendor-specific extended query addresses (word mode) addresses (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0031h minor version number, ascii 45h 8ah 0000h address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0004h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 04 = 29lv800 mode 4ah 94h 0000h simultaneous operation 00 = not supported 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 000xh top/bottom boot sector flag 02h = bottom boot device, 03h = top boot device
december 14, 2005 am29lv320d 25 datasheet command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. table 14 on page 29 defines the valid register command sequences. note that writing incor- rect address and data values or writing them in the im- proper sequence may place the device in an unknown state. a reset command is required to return the de- vice to normal operation. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. after completing a pro- gramming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume com- mands? on page 28 for more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase op- eration, or if the device is in the autoselect mode. see the next section, ?reset command , for more informa- tion. see also ?requirements for reading array data? on page 11 for more information. the read-only opera- tions table provides the read parameters, and figure 14, on page 38 shows the timing diagram. reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to which the system was writing to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to which the system was writing to the read mode. if the program command sequence is written to a sector that is in the erase suspend mode, writing the reset command returns the device to the erase-sus- pend-read mode. once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the de- vice entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). autoselect command sequence the autoselect command sequence allows the host system to read several identifier codes at specific ad- dresses: table 13. autoselect codes table 14 on page 29 shows the address and data re- quirements. this method is an alternative to that shown in table 6 on page 16, which is intended for prom programmers and requires v id on address pin a9. the autoselect command sequence may be writ- ten to an address within sector that is either in the read or erase-suspend-read mode. the autoselect com- mand may not be written while the device is actively programming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect command sequence. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in erase suspend). enter secured silicon sector/exit secured silicon sector command sequence the secured silicon sector provides a secured data area containing a random, sixteen-byte electronic se- rial number (esn). the system can access the se- cured silicon sector by issuing the three-cycle enter secured silicon sector command sequence. the de- vice continues to access the secured silicon sector until the system issues the four-cycle exit secured sil- identifier code address manufacturer id 00h device id 01h secured silicon sector factory protect 03h sector group protect verify (sa)02h
26 am29lv320d december 14, 2005 datasheet icon sector command sequence. the exit secured sil- icon sector command sequence returns the device to normal operation. table 14 on page 29 shows the ad- dress and data requirements for both command se- quences. note that the acc function and unlock bypass modes are not available when the device en- ters the secured silicon sector. see also ?secured sil- icon sector flash memory region? on page 20 for further information. byte/word program command sequence the system may program the device by word or byte, depending on the state of the byte# pin. program- ming is a four-bus-cycle operation. the program com- mand sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the pro- grammed cell margin. table 14 on page 29 shows the address and data requirements for the byte program command sequence. note that the autoselect, se- cured silicon sector, and cfi modes are unavailable while a programming operation is in progress. when the embedded program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7, dq6, or ry/by#. refer to ?write operation sta- tus? on page 30 for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once the device returns to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was suc- cessful. however, a succeeding read shows that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to pro- gram bytes or words to the device faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass pro- gram command, a0h; the second cycle contains the program address and data. additional data is pro- grammed in the same manner. this mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. table 14 on page 29 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the data 90h. the second cycle need only contain the data 00h. the device then re turns to the read mode. the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en- ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/acc pin must not be at v hh any operation other than accelerated programming, or device dam- age may result. in addition, the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. figure 4, on page 27 illustrates the algorithm for the program operation. refer to the table ?erase and pro- gram operations? on page 41 for parameters, and fig- ure 18, on page 42 for timing diagrams.
december 14, 2005 am29lv320d 27 datasheet figure 4. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 14 on page 29 shows the address and data requirements for the chip erase command sequence. note that the au- toselect, secured silicon sector, and cfi modes are unavailable while an erase operation is in progress. when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to ?write operation status? on page 30 for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that oc- curs, the chip erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. figure 5, on page 28 illustrates the algorithm for the erase operation. refer to table ?erase and program operations? on page 41 for parameters, and figure 19, on page 43 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. table 14 on page 29 shows the address and data requirements for the sec- tor erase command sequence. note that the autose- lect, secured silicon sector, and cfi modes are unavailable while an erase operation is in progress. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise the last address and command may not be accepted, and erasure may begin. it is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets the device to the read mode. the system must rewrite the command se- quence and any additional addresses and commands. the system can monitor dq3 to determine if the sec- tor erase timer timed out (see the section ?dq3: sec- tor erase timer? on page 32.). the time-out begins from the rising edge of the final we# pulse in the com- mand sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by reading dq7, dq6, start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 14 on page 29 for program command sequence.
28 am29lv320d december 14, 2005 datasheet dq2, or ry/by# in the erasing sector. refer to ?write operation status? on page 30 for information on these status bits. once the sector erase operation begins, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device returns to read- ing array data, to ensure data integrity. figure 5, on page 28 illustrates the algorithm for the erase operation. refer to table ?erase and program operations? on page 41 for parameters, and figure 19, on page 43 for timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sec- tor erase operation, including the 50 s time-out pe- riod during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a max- imum of 20 s to suspend the erase operation. how- ever, when the erase suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. after the erase operation is suspended, the device en- ters the erase-suspend-read mode. the system can read data from or program data to any sector not se- lected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces status infor- mation on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is ac- tively erasing or is erase-suspended. refer to the ?write operation status? on page 30 section for infor- mation on these status bits. after an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard byte program operation. refer to ?write operation status? on page 30 for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to ?autoselect mode? on page 16 and ?autoselect com- mand sequence? on page 25 for details. to resume the sector erase operation, the system must write the erase resume command. further writes of the resume command are ignored. another erase suspend command can be written after the chip resumes erasing. figure 5. erase operation start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 14 on page 29 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
december 14, 2005 am29lv320d 29 datasheet command definitions table 14. am29lv320d command definitions legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a20?a12 uniquely select any sector. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a20?a11 are don?t cares. 6. no unlock or command cycles required when device is in read mode. 7. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when a device is in the autoselect mode, or if dq5 goes high (while the device is providing status information). 8. the fourth cycle of the autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. see the autoselect command sequence section for more information. 9. the data is 99h for factory locked and 19h for not factory locked. 10. the data is 00h for an unprotected sector and 01h for a protected sector. 11. the unlock bypass command is required prior to the unlock bypass program command. 12. the unlock bypass reset command is required to return to the read mode when the device is in the unlock bypass mode. 13. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 14. the erase resume command is valid only during the erase suspend mode. 15. command is valid when device is ready to read array data or when device is in autoselect mode. command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id word 4 555 aa 2aa 55 555 90 x00 01 byte aaa 555 aaa device id word 4 555 aa 2aa 55 555 90 x01 (see table 6) byte aaa 555 aaa x02 secured silicon factory protect (note 9) word 4 555 aa 2aa 55 555 90 x03 99/19 byte aaa 555 aaa x06 sector protect verify (note 10) word 4 555 aa 2aa 55 555 90 (sa)x02 00/01 byte aaa 555 aaa (sa)x04 enter secured silicon sector word 3 555 aa 2aa 55 555 88 byte aaa 555 aaa exit secured silicon sector word 4 555 aa 2aa 55 555 90 xxx 00 byte aaa 555 aaa program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa unlock bypass word 3 555 aa 2aa 55 555 20 byte aaa 555 aaa unlock bypass program (note 11) 2 xxx a0 pa pd unlock bypass reset (note 12) 2 xxx 90 xxx 00 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase suspend (note 13) 1 xxx b0 erase resume (note 14) 1 xxx 30 cfi query (note 15) word 1 55 98 byte aa
30 am29lv320d december 14, 2005 datasheet write operation status the device provides several bits to determine the sta- tus of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 15 on page 33 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an em- bedded program or erase operation is in progress or is completed. dq7: data# polling the data# polling bit, dq7, indicates to the host sys- tem whether an embedded program or erase algo- rithm is in progress or completed, or whether a device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command se- quence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. this dq7 status also applies to pro- gramming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# poll- ing on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. however, if the sys- tem reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device completes the program or erase operation and dq7 contains valid data, the data output s on dq0?dq6 may be still invalid. valid data on dq0?dq7 appears on succes- sive read cycles. table 15 on page 33 shows the outputs for data# poll- ing on dq7. figure 6, on page 30 shows the data# polling algorithm. figure 20, on page 44 in the ac characteristics section shows the data# polling timing diagram. figure 6. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?q0 addr = va read dq7?q0 addr = va dq7 = data? start notes: 1. va = valid address for prog ramming. during a sector erase operation, a valid addres s is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
december 14, 2005 am29lv320d 31 datasheet ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively eras- ing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. table 15 on page 33 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or com- plete, or whether the device entered the erase sus- pend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 tog- gles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are pro- tected. the system can use dq6 and dq2 together to deter- mine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase sus- pend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on ?dq7: data# polling? on page 30). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 15 on page 33 shows the outputs for toggle bit i on dq6. figure 7, on page 31 shows the toggle bit al- gorithm. figure 21, on page 45 in the ?ac characteris- tics? section shows the toggle bit timing diagrams. figure 22, on page 45 shows the differences between dq2 and dq6 in graphical form. see also the subsec- tion on dq2: toggle bit ii . figure 7. toggle bit algorithm dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?q0 toggle bit = toggle? read dq7?q0 twice read dq7?q0 note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
32 am29lv320d december 14, 2005 datasheet or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that were selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is ac- tively erasing, or is in erase suspend, but cannot dis- tinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode infor- mation. refer to table 15 on page 33 to compare out- puts for dq2 and dq6. figure 7, on page 31 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? on page 31 explains the algorithm. see also the dq6: toggle bit i subsection. figure 21, on page 45 shows the toggle bit timing diagram. figure 22, on page 45 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 7, on page 31 for the following discus- sion. whenever the system initially begins reading tog- gle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typi- cally, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device completed the program or erase operation. the sys- tem can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device successfully completed the pro- gram or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of figure 7, on page 31 ). dq5: exceeded timing limits dq5 indicates whether the program or erase time ex- ceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit is exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if the device was previ- ously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure started. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between addi- tional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm started; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the de- vice accepts additional sector erase commands. to ensure the command is accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 15 on page 33 shows the status of dq3 relative to the other status bits.
december 14, 2005 am29lv320d 33 datasheet table 15. write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation exceeds the ma ximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status info rmation. refer to the appropriate subsection for further details. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
34 am29lv320d december 14, 2005 datasheet absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . ?65 c to +125 c voltage with respect to ground v cc (note 1). . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v a9 , oe# , reset#, and wp#/acc (note 2) . . . . . . . ?0.5 v to +12.5 v all other pins (note 1) . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 8, on page 34 . during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 9, on page 34 . 2. minimum dc input voltage on pins a9, oe#, reset#, and wp#/acc is ?0.5 v. during voltage transitions, a9, oe#, wp#/acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 8, on page 34 . maximum dc input voltage on pin a9 is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. maximum dc input voltage on wp#/acc is +9.5 v which may overshoot to +12.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for exten ded periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40 c to +85 c v cc supply voltages v cc for all devices . . . . . . . . . . . . . . . . . 2.7 v to 3.6 v operating ranges de fine those limits between which the functionality of the device is guaranteed. 20 ns 20 ns +0.8 v v ss ?0.5 v 20 ns v ss ?2.0 v figure 8. maximum negative overshoot waveform figure 9. maximum positive overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
december 14, 2005 am29lv320d 35 datasheet dc characteristics cmos compatible notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc = v cc max. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 5. not 100% tested. parameter symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 3.0 a i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lr reset# input load current v cc = v cc max ; reset# = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (notes 1, 2) ce# = v il, oe# = v ih , byte mode 5 mhz 10 16 ma 1 mhz 2 4 ce# = v il, oe# = v ih , word mode 5 mhz 10 16 1 mhz 2 4 i cc2 v cc active write current (notes 2, 3) ce# = v il, oe# = v ih , we# = v il 15 30 ma i cc3 v cc standby current (note 2) ce#, reset# = v cc 0.3 v 0.2 5 a i cc4 v cc reset current (note 2) reset# = v ss 0.3 v 0.2 5 a i cc5 automatic sleep mode (notes 2, 4) v ih = v cc 0.3 v; v il = v ss 0.3 v 0.2 5 a v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v v hh voltage for wp#/acc sector protect/unprotect and program acceleration v cc = 3.0 v 10% 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0 v 10% 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = ?100 a, v cc = v cc min v cc ?0.4 v lko low v cc lock-out voltage (note 5) 2.3 2.5 v
36 am29lv320d december 14, 2005 datasheet dc characteristics zero-power flash note: addresses are switching at 1 mhz figure 10. i cc1 current vs. time (showing active and automatic sleep currents) 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 10 8 2 0 1 2345 frequency in mhz supply current in ma note: t = 25 c figure 11. typical i cc1 vs. frequency 2.7 v 3.6 v 4 6 12
december 14, 2005 am29lv320d 37 datasheet test conditions table 16. test specifications key to switching waveforms 2.7 k c l 6.2 k 3.3 v device under te s t note: diodes are in3064 or equivalent figure 12. test setup test condition 90 120 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 1.5 v output measurement level input figure 13. input waveforms and measurement levels
38 am29lv320d december 14, 2005 datasheet ac characteristics read-only operations notes: 1. not 100% tested. 2. see figure 12, on page 37 and table 16 on page 37 for test specifications. parameter description test setup speed options jedec std. 90 120 unit t avav t rc read cycle time (note 1) min 90 120 ns t avqv t acc address to output delay ce#, oe# = v il max 90 120 ns t elqv t ce chip enable to output delay oe# = v il max 90 120 ns t glqv t oe output enable to output delay max 40 50 ns t ehqz t df chip enable to output high z (note 1) max 16 ns t ghqz t df output enable to output high z (note 1) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df figure 14. read operation timings
december 14, 2005 am29lv320d 39 datasheet ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb t rh figure 15. reset timings
40 am29lv320d december 14, 2005 datasheet ac characteristics word/byte configuration (byte#) parameter 90 120 jedec std. description unit t elfl/ t elfh ce# to byte# switching low or high max 5 ns t flqz byte# switching low to output high z max 16 ns t fhqv byte# switching high to output active min 90 120 ns dq15 output data output (dq0?dq7) ce# oe# byte# t elfl dq0?dq14 data output (dq0?dq14) dq15/a-1 address input t flqz byte# switching from word to byte mode dq15 output data output (dq0?dq7) byte# t elfh dq0?dq14 data output (dq0?dq14) dq15/a-1 address input t fhqv byte# switching from byte to word mode figure 16. byte# timings for read operations note: refer to the erase/program operations table for t as and t ah specifications. figure 17. byte# timings for write operations ce# we# byte# the falling edge of the last we# signal t hold (t ah ) t set (t as )
december 14, 2005 am29lv320d 41 datasheet ac characteristics erase and program operations notes: 1. not 100% tested. 2. see ?erase and programming performance? on page 50 for more information. parameter 90 120 jedec std. description unit t avav t wc write cycle time (note 1) min 90 120 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 50 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 50 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 50 ns t whdl t wph write pulse width high min 30 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 2) byte typ 9 s word typ 11 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) ty p 7 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec t vcs v cc setup time (note 1) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns
42 am29lv320d december 14, 2005 datasheet ac characteristics oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa n otes: 1 . pa = program address, pd = program data, d out is the true data at the program address. 2 . illustration shows device in word mode. figure 18. program operation timings
december 14, 2005 am29lv320d 43 datasheet ac characteristics oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy notes: 1. sa = sector address (for sector erase) , va = valid address for reading status data (see ?write operation status? on page 30). 2 . these waveforms are for the word mode. figure 19. chip/sector erase operation timings
44 am29lv320d december 14, 2005 datasheet ac characteristics we# ce# oe# high z t oe high z dq7 dq0?q6 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc note: va = valid address. illustration shows fi rst status cycle after command sequence, la st status read cycle, and array data read cycle. figure 20. data# polling timings (during embedded algorithms)
december 14, 2005 am29lv320d 45 datasheet ac characteristics oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# note: va = valid address; not r equired for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 21. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase- suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 22. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
46 am29lv320d december 14, 2005 datasheet ac characteristics temporary sector unprotect note: not 100% tested. figure 24. accelerated program timing diagram parameter all speed options jedec std. description unit t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb figure 23. temporary sector unprotect timing diagram wp#/acc t vhh v hh v il or v ih v il or v ih t vhh
december 14, 2005 am29lv320d 47 datasheet ac characteristics sector/sector block protect: 150 ?, sector/sector block unprot ect: 15 ms 1 ? reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector/sector block protect or unprotect verify v id v ih * for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unpr otect, a6 = 1, a1 = 1, a0 = 0. figure 25. sector/sector block protect and unprotect timing diagram
48 am29lv320d december 14, 2005 datasheet ac characteristics alternate ce# controlled erase and program operations notes: 1. not 100% tested. 2. see ?erase and programming performance? on page 50 for more information. parameter 90 120 jedec std. description unit t avav t wc write cycle time (note 1) min 90 120 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 50 ns t dveh t ds data setup time min 45 50 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 50 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 programming operation (note 2) byte typ 9 s word typ 11 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) ty p 7 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec
december 14, 2005 am29lv320d 49 datasheet ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycl es of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. figure 26. alternate ce# controlled write (erase/program) operation timings
50 am29lv320d december 14, 2005 datasheet erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 1,000,000 cycles. additionally, programming typicals assu me checkerboard pattern. 2. under worst case conditions of 90 c, v cc = 2.7 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 14 on page 29 for further information on command definitions. 6. the device has a minimum erase and pr ogram cycle endurance of 1,000,000 cycles. latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. tsop and bga package capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter typ (note 1) max (note 2) unit comments sector erase time 0.7 15 sec excludes 00h programming prior to erasure (note 4) chip erase time 50 sec byte program time 9 300 s excludes system level overhead (note 5) word program time 11 360 s accelerated byte/word program time 7 210 s chip program time (note 3) byte mode 36 108 sec word mode 24 72 description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 6 7.5 pf fine-pitch bga 4.2 5.0 pf c out output capacitance v out = 0 tsop 8.5 12 pf fine-pitch bga 5.4 6.5 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf fine-pitch bga 3.9 4.7 pf parameter description t est conditions min unit minimum pattern data retention time 150 c10years 125 c20years
december 14, 2005 am29lv320d 51 datasheet physical dimensions fbd048?48-ball fine-pitch ball grid array (fbga) 6x12mm package dwg rev af; 1/2000 xfbd 048 6.00 mm x 12.00 mm package 1.20 0.20 0.84 0.94 12.00 bsc 6.00 bsc 5.60 bsc 4.00 bsc 8 6 48 0.25 0.30 0.35 0.80 bsc 0.40 bsc
52 am29lv320d december 14, 2005 datasheet physical dimensions ts 048?48-pin standard tsop dwg rev aa; 10/99
december 14, 2005 am29lv320d 53 datasheet revision summary revision a (november 1, 2000) initial release. revision a+1 (january 23, 2001) ordering information corrected fbga part number table to include bottom boot part numbers. revision a+2 (february 1, 2001) connection diagrams corrected fbga ball matrix. revision a+3 (july 2, 2001) global changed data sheet status from advance information to preliminary. table 3, top boot secured silicon sector addresses corrected sector block size for sa60?sa62 to 3x64. sector/sector block protection and unprotection noted that sectors are erased in parallel. secured silicon sector flash memory region noted changes for upcoming versions of these de- vices: reduced secured silicons ector size, different esn location for top boot devices, and deletion of se- cured silicon erase functionality. current versions of these devices remain unaffected. revision b (july 12, 2002) global deleted preliminary status from document. ordering information deleted burn-in option. table 1, am29lv320d device bus operations in the legend, corrected v hh maximum voltage to 12.5 v. secured silicon sector flash memory region added description of secured silicon protection verifi- cation. autoselect command sequence clarified description of function. table 14, am29lv320d command definitions corrected autoselect codes for secured silicon fac- tory protect. erase and program operations table corrected to indicate t busy specification is a maximum value. revision b+1 (july 30, 2002) figure 3, secured silicon sector protect verify deleted fifth block in flowchart and modified text in fourth block. revision c (october 25, 2002) distinctive characteristics changed endurance from ?write? to ?erase? cycles. connection diagrams deleted ultrasonic reference and added package types to special package handling text. ordering information added commercial temperature range and removed extended temperature range. secured silicon flash memory region customer lockable subsection: deleted reference to alternate method of sector protection. command definitions noted the following: autoselect, secured silicon, and cfi functions are not available during a program or erase operation. acc and unlock bypass modes are not available when the secured silicon sector is enabled. writing incorrect data or commands may place the de- vice in an unknown state. a reset command is then re- quired. ac characteristics read-only operations; word/byte configuration: changed t df and t flqz to 16 ns for all speed options. dc characteristics deleted i acc and added i lr specifications from table. tsop, so, and bga package capacitance added bga capacitance to table. revision c+1 (february 16, 2003) distinctive characteristics added reference to mirrorbit in secured silicon sec- tion. added sector architecture section. secured silicon flash memory region referenced mirrorbit for an example in last sentence of first paragraph.
54 am29lv320d december 14, 2005 datasheet command definitions changed the first address of the unlock bypass reset from ba to xxx. erase and programming performance corrected the sector erase time typical to 0.7. revision c+2 (april 4, 2003) distinctive characteristics clarified reference to mirrorbit in secured silicon sec- tion. secured silicon sector clarified reference of mirrorbit for an example in last sentence of first paragraph. revision c+3 (september 19, 2003) valid combinations added the 90r package to table. revision c+4 (april 5, 2004) command definitions changed first address data for erase suspend/re- sume from ba to xxx. revision c+5 (june 4, 2004) ordering information added lead-free (pb-free) options to the temperature ranges breakout table and valid combinations table. product selector guide added 90r voltage range. revision c+6 (november 15, 2004) global added colophon. updated trademarks. added refer- ence links ordering information added automotive in-cabin temperature range and associated part numbers in the valid combination ta- ble. erase and programming performance updated chip erase time. ac characteristics added t rh line to figure 15. erase and program operations corrected sector erase operation time ( t whwh2) alternate ce# control erase and program operations corrected sector erase operation time ( t whwh2) command definitions update text in sector erase command sequence paragraph. revision c+7 (july 11, 2005) global added text to first page of data sheet and cover page indicating that the am29lv320d is now superceded by the s29al032d device. replaced all occurences of ?secsi sector? with ?se- cured silicon sector? to reflect change of terminology. common flash memory interfacte (cfi) added reference to application note. deleted link to cfi documents available on the world wide web. revision c+8 (december 14, 2005) global this product has been retired and is not available for designs. for new and current designs, s29al032d supersedes am29lv320d and is the factory-recom- mended migration path. please refer to the s29al032d datasheet for specifications and ordering information. availability of this document is retained for reference and historical purposes only.
december 14, 2005 am29lv320d 55 datasheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufac tured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a seri ous effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion llc will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any se miconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on expor t under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. trademarks copyright ? 2000-2005 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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